The invention relates to a flash memory arrangement comprising a first memory cell for the non-volatile memory of information and a read-write circuit. The read-write circuit comprises a write latch, a read amplifier, a bit-circuit pre-charging circuit, and a databus interface. Here the first memory cell is connected to a first bit circuit, a word circuit, a VSE circuit, and a select circuit, and the read-write circuit to a column decode, a databus, and a read control signal circuit.
Here, the gate control circuit of the memory transistor is called the VSE circuit. As the only hub of the flash memory arrangement, it carries a “high level voltage,” described in the following in the writing process on page 8 . . .
One and two-transistor cells are known, which require high voltages at drain and gate for generating hot electrons and storing them in the memory transistor.
Additionally, two-transistor cells are known which operate in a voltage-controlled fashion, in which high voltages on the bit circuits must be generated and decoded, with here not all bit circuits and/or every pair of bit circuits comprising a separate read amplifier.
The principle of a read amplifier and its arrangement in the array are known from WO 03/036651.
The information from the bit circuit is forwarded with information from the column decoder to a pre-amplifier, and only then amplified in the read amplifier, with the reference path with the reference cell and the reference pre-amplifier not being a part of the flash array.
A NOR-flash array with a high-voltage program buffer memory and a low-speed page read amplifier and input signals for the read amplifier controlled by a low voltage y-decoder is known from WO 2011/005665. Here, the programing and thus the decoding occurs with high voltages on the bit circuits and select circuits up to 8V.
The disadvantages of prior art are given in that the known solutions in the read-write path operate with voltages ranging from 5 to 8V, here called high voltage, which requires appropriately large transistors and thus larger chip areas, increased decoding expense, and slower access times. This also leads to limitations for the range of operating voltages and temperatures.
The invention is based on the objective to overcome the disadvantages of prior art.